08618649 is referenced by 43 patents and cites 263 patents.

A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.

Title
Compliant printed circuit semiconductor package
Application Number
13/318263
Publication Number
8618649 (B2)
Application Date
May 27, 2010
Publication Date
December 31, 2013
Inventor
James Rathburn
Mound
MN, US
Agent
Stoel Rives
Assignee
HSIO Technologies
MN, US
IPC
H01L 23/52
H01L 23/48
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