08595671 is referenced by 13 patents and cites 17 patents.

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of Vdd, multiple voltage thresholding Vt, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi Vdd FPGA.

Title
Low-power FPGA circuits and methods
Application Number
12/773686
Publication Number
8595671 (B2)
Application Date
May 4, 2010
Publication Date
November 26, 2013
Inventor
Lei He
Irvine
CA, US
Agent
John P O Banion
Assignee
The Regents of the University of California
CA, US
IPC
G06F 17/50
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