08566666 is referenced by 7 patents and cites 110 patents.

Various embodiments of the present invention provide systems and methods for min-sum based decoding of non-binary LDPC codes. For example, a non-binary low density parity check data decoding system is discussed that includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node message vectors and to calculate perceived values based on check node to variable node message vectors. The check node processor is operable to generate the check node to variable node message vectors and to calculate checksums based on variable node to check node message vectors. The check node processor includes a minimum and subminimum finder circuit operable to process a plurality of sub-messages in each variable node to check node message vector. The check node processor also includes a select and combine circuit operable to combine an output of the minimum and subminimum finder circuit to generate the check node to variable node message vectors.

Title
Min-sum based non-binary LDPC decoder
Application Number
13/180495
Publication Number
8566666 (B2)
Application Date
July 11, 2011
Publication Date
October 22, 2013
Inventor
Shaohua Yang
San Jose
CA, US
Zongwang Li
San Jose
CA, US
Chung Li Wang
San Jose
CA, US
Agent
Hamilton DeSanctis & Cha
Assignee
LSI Corporation
CA, US
IPC
H03M 13/11
H03M 13/00
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