08463832 is referenced by 1 patents and cites 4 patents.

Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.

Title
Digital signal processing block architecture for programmable logic device
Application Number
12/146042
Publication Number
8463832 (B1)
Application Date
June 25, 2008
Publication Date
June 11, 2013
Inventor
Satwant Singh
Fremont
CA, US
Ian Ing
San Jose
CA, US
Asher Hazanchuk
Sunnyvale
CA, US
Assignee
Lattice Semiconductor Corporation
OR, US
IPC
G06F 7/38
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