08420519 is referenced by 3 patents and cites 7 patents.

Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

Title
Methods for fabricating integrated circuits with controlled P-channel threshold voltage
Application Number
13/286292
Publication Number
8420519 (B1)
Application Date
November 1, 2011
Publication Date
April 16, 2013
Inventor
Klaus Hempel
Dresden
DE
Elke Erben
Dresden
DE
Dina Triyoso
Dresden
DE
Agent
Ingrassia Fisher & Lorenz P C
Assignee
GLOBALFOUNDRIES
KY
IPC
H01L 21/283
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