08402403 cites 20 patents.

A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis.

Title
Verifying a register-transfer level design of an execution unit
Application Number
12/946325
Publication Number
8402403 (B2)
Application Date
November 15, 2010
Publication Date
March 19, 2013
Inventor
Kai Weber
Holzgerlingen
DE
Juergen Vielfort
Althengstett
DE
Michelangelo Masini
Fellbach
DE
Stefan Letz
Boeblingen
DE
Agent
Libby Z Toub
Stephen J Walder Jr
Francis Lammes
Assignee
International Business Machines Corporation
NY, US
IPC
G06G 7/62
G06F 9/455
G06F 17/50
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