08385117 is referenced by 26 patents and cites 15 patents.

A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio.

Title
Semiconductor memory device and decoding method
Application Number
13/233530
Publication Number
8385117 (B2)
Application Date
September 15, 2011
Publication Date
February 26, 2013
Inventor
Hironori Uchikawa
Kanagawa
JP
Kenji Sakurada
Kanagawa
JP
Agent
Oblon Spivak McClelland Maier & Neustadt L
Assignee
Kabushiki Kaisha Toshiba
JP
IPC
G11C 16/04
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