08359522 is referenced by 39 patents and cites 206 patents.

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Title
Low density parity check decoder for regular LDPC codes
Application Number
12/113729
Publication Number
8359522 (B2)
Application Date
May 1, 2008
Publication Date
January 22, 2013
Inventor
Gwan S Choi
College Station
TX, US
Kiran K Gunnam
San Jose
CA, US
Agent
Conley Rose P C
Assignee
Texas A&M University System
TX, US
IPC
G06F 11/00
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