08249848 is referenced by 3 patents and cites 10 patents.

An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

Title
Verifying a processor design using a processor simulation model
Application Number
12/182211
Publication Number
8249848 (B2)
Application Date
July 30, 2008
Publication Date
August 21, 2012
Inventor
Juergen Vielfort
Althengstett
DE
Kai Weber
Holzgerlingen
DE
Stefan Letz
Boeblingen
DE
Agent
Cynthia seal
The Steadman Law Firm PLLC
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 17/50
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