08200883 is referenced by 3 patents and cites 20 patents.

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Title
Micro-tile memory interfaces
Application Number
13/114903
Publication Number
8200883 (B2)
Application Date
May 24, 2011
Publication Date
June 12, 2012
Inventor
Douglas Gabel
Hillsboro
OR, US
James Akiyama
Beaverton
OR, US
Peter MacWilliams
Aloha
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 12/00
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