Stacked semiconductor package having discrete components United States Patent 08174105

08174105 is referenced by 25 patents and cites 136 patents.

A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess, and a discrete component contained in the recess encapsulated in a die attach polymer. The stacked semiconductor package also includes interconnects electrically connecting the semiconductor dice and discrete components, and an encapsulant encapsulating the dice and the interconnects.

Title
Stacked semiconductor package having discrete components
Application Number
13/110275
Publication Number
8174105 (B2)
Application Date
May 18, 2011
Publication Date
May 8, 2012
Inventor
Chia Yong Poo
Singapore
SG
Chua Swee Kwang
Singapore
SG
Agent
Stephen A Gratton
Assignee
Micron Technology
ID, US
IPC
H01L 23/02
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Citations: 25 (view full list)

  1. Michael S Smith: System, method, and computer program product for improving memory systems. P4TENTS1, Patrick E Caldwell Esq, The Caldwell Firm, August 30, 2016: US09432298 (130 worldwide citation)
  2. Michael S Smith: Multiple class memory systems. P4tents1, Patrick E Caldwell Esq, The Caldwell Firm, January 6, 2015: US08930647 (57 worldwide citation)
  3. Michael S Smith: User interface system, method, and computer program product. P4TENTS1, Patrick E Caldwell Esq, The Caldwell Firm, August 16, 2016: US09417754 (48 worldwide citation)
  4. Sheldon Terry Schwandt, Farzin Dehmoubed, James Carl Infanti, James Randolph Winter Lepp, Oleg Los: Universal integrated circuit card apparatus and related methods. Blackberry, Haley Flight & Zimmerman, February 11, 2014: US08649820 (39 worldwide citation)
  5. James Randolph Winter Lepp, Jean Philippe Paul Cormier, Sheldon Terry Schwandt, Oleg Los, Petra Braun: UICC apparatus and related methods. BlackBerry, Hanley Flight & Zimmerman, January 20, 2015: US08936199 (13 worldwide citation)
  6. Michael S Smith: Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory. P4TENTS1, Patrick E Caldwell Esq, The Caldwell Firm, October 13, 2015: US09158546 (3 worldwide citation)
  7. Michael S Smith: Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system. P4TENTS1, Patrick E Caldwell Esq, The Caldwell Firm, November 3, 2015: US09176671 (3 worldwide citation)
  8. Michael S Smith: System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class. P4TENTS1, Patrick E Caldwell Esq, The Caldwell Firm, November 10, 2015: US09182914 (3 worldwide citation)
  9. Michael S Smith: Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system. P4TENTS1, Patrick E Caldwell Esq, The Cladwell Firm, November 17, 2015: US09189442 (2 worldwide citation)
  10. Michael S Smith: System, method and computer program product for fetching data between an execution of a plurality of threads. P4TENTS1, Patrick E Caldwell Esq, The Caldwell Firm, December 29, 2015: US09223507 (2 worldwide citation)

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