08134184 is referenced by 137 patents and cites 412 patents.

A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout corresponding to an entire gate level of the cell. The gate electrode layout includes a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell.

Title
Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion
Application Number
12/567641
Publication Number
8134184 (B2)
Application Date
September 25, 2009
Publication Date
March 13, 2012
Inventor
Michael C Smayling
San Jose
CA, US
Scott T Becker
San Jose
CA, US
Agent
Martine Penilla Group
Assignee
Tela Innovations
CA, US
IPC
H01L 27/10
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