08129234 is referenced by 5 patents and cites 3 patents.

A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.

Title
Method of forming bipolar transistor integrated with metal gate CMOS devices
Application Number
12/556205
Publication Number
8129234 (B2)
Application Date
September 9, 2009
Publication Date
March 6, 2012
Inventor
Phung T Nguyen
Hopewell Junction
NY, US
Daniel J Jaeger
Hopewell Junction
NY, US
Ebenezer E Eshun
Hopewell Junction
NY, US
Thomas A Wallner
Hopewell Junction
NY, US
Agent
H Daniel Schnurmann
Scully Scott Murphy & Presser P C
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/8249
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