08120966 is referenced by 13 patents and cites 77 patents.

A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and erasing, erase verifying, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state. Other block sections are iteratively selected and erased, erased verified, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

Title
Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory
Application Number
12/658121
Publication Number
8120966 (B2)
Application Date
February 3, 2010
Publication Date
February 21, 2012
Inventor
Peter Wung Lee
Saratoga
CA, US
Agent
Billy Knowles
Stephen B Ackerman
Saile Ackerman
Assignee
Aplus Flash Technology
CA, US
IPC
G11C 11/34
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