08099523 is referenced by 13 patents and cites 43 patents.

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Title
PCI express enhancements and extensions including transactions having prefetch parameters
Application Number
13/73219
Publication Number
8099523 (B2)
Application Date
March 28, 2011
Publication Date
January 17, 2012
Inventor
Doron Shamia
Modiin
IL
Eliezer Weissmann
Haifa
IL
Eran Tamari
Ramat Gan
IL
Ilan Pardo
Ramat-Hasharon
IL
Abraham Mendelson
Haifa
IL
Ohad Falik
Kfar-Saba
IL
Robert Blankenship
Tacoma
WA, US
James Akiyama
Beaverton
OR, US
Sridhar Muthrasanallur
Puyallup
WA, US
Anil Vasudevan
Portland
OR, US
Scott Dion Rodgers
Hillsboro
OR, US
Peter Barry
Ardnacrusha
IE
Ajay Bhatt
Portland
OR, US
Mark Rosenbluth
Uxbridge
MA, US
David Harriman
Portland
OR, US
Debendra Das Sharma
Santa Clara
CA, US
Prashant Sethi
Folsom
CA, US
Mahesh Wagh
Portland
OR, US
Jasmin Ajanovic
Portland
OR, US
Agent
David P McAbee
Assignee
Intel Corporation
CA, US
IPC
G06F 3/00
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