08053340 is referenced by 80 patents and cites 7 patents.

A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Title
Method for fabricating semiconductor devices with reduced junction diffusion
Application Number
11/862213
Publication Number
8053340 (B2)
Application Date
September 27, 2007
Publication Date
November 8, 2011
Inventor
Lap Chan
Singapore
SG
Bangun Indajang
Singapore
SG
Francis Benistant
Singapore
SG
Sai Hooi Yeong
Singapore
SG
Benjamin Colombeau
Singapore
SG
Agent
Horizon IP
Assignee
Globalfoundries Singapore
SG
National University of Singapore
SG
IPC
H01L 21/38
H01L 21/22
H01L 21/425
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