08053281 is referenced by 1 patents and cites 6 patents.

A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.

Title
Method of forming a wafer level package
Application Number
12/315855
Publication Number
8053281 (B2)
Application Date
December 4, 2008
Publication Date
November 8, 2011
Inventor
Guilian Gao
San Jose
CA, US
Charles Rosenstein
Ramat Beit Shemesh
IL
David Ovrutsky
Charlotte
NC, US
Belgacem Haba
Saratoga
CA, US
Kenneth Allen Honer
Santa Clara
CA, US
Agent
Lerner David Littenberg Krumholz & Mentlik
Assignee
Tessera
CA, US
IPC
H01L 21/00
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