07987222 is referenced by 1 patents and cites 14 patents.

A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first number and a second plurality of bits from the second number is retrieved. The product is scaled with respect to a position of the first plurality of bits from the first number and a position of the first plurality of bits from the second number. The stored value is scaled with respect to a position of the second plurality of bits from the second number and a position of the second plurality of bits from the second number. The scaled product and the scaled stored value are summed.

Title
Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension
Application Number
10/829559
Publication Number
7987222 (B1)
Application Date
April 22, 2004
Publication Date
July 26, 2011
Inventor
Benjamin Esposito
Oviedo
FL, US
Asher Hazanchuk
Sunnyvale
CA, US
Agent
L Cho
Assignee
Altera Corporation
CA, US
IPC
G06F 7/38
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