07974030 is referenced by 4 patents and cites 70 patents.

Various embodiments of the present invention provide systems and methods for providing a corrected dibit signal. As an example, various embodiments of the present invention provide dibit correction circuits. Such dibit correction circuits include a dibit sample buffer, a maximum sample detector circuit, a side sample detector circuit, and a dibit correction circuit. The dibit sample buffer includes a plurality of samples of an uncorrected dibit signal. The maximum sample detector circuit identifies a maximum sample of the plurality of samples of the uncorrected dibit signal, and the side sample detector circuit identifies a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal. The dibit correction circuit applies a correction factor calculated based at least in part on the maximum sample, the first side sample and the second side sample to at least a subset of the plurality of samples of the uncorrected dibit signals to yield a plurality of corrected dibit signals.

Title
Systems and methods for dibit correction
Application Number
12/463626
Publication Number
7974030 (B2)
Application Date
May 11, 2009
Publication Date
July 5, 2011
Inventor
Yuan Xing Lee
San Jose
CA, US
Hongwei Song
Longmont
CO, US
George Mathew
San Jose
CA, US
Agent
Hamilton DeSanctis & Cha
Assignee
LSI Corporation
CA, US
IPC
G11B 20/10
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