07962867 is referenced by 164 patents and cites 143 patents.

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Title
Electronic design for integrated circuits based on process related variations
Application Number
12/21298
Publication Number
7962867 (B2)
Application Date
January 28, 2008
Publication Date
June 14, 2011
Inventor
Taber H Smith
San Jose
CA, US
David White
San Jose
CA, US
Agent
Vista IP Law Group
Assignee
Cadence Design Systems
CA, US
IPC
G06F 17/50
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