07956421 is referenced by 101 patents and cites 269 patents.

A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.

Title
Cross-coupled transistor layouts in restricted gate level layout architecture
Application Number
12/402465
Publication Number
7956421 (B2)
Application Date
March 11, 2009
Publication Date
June 7, 2011
Inventor
Scott T Becker
Scotts Valley
CA, US
Agent
Martine Penilla & Gencarella
Assignee
Tela Innovations
CA, US
IPC
H01L 27/08
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