07932545 is referenced by 125 patents and cites 268 patents.

A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Within a five wavelength photolithographic interaction radius within the gate electrode level region, a width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. The conductive features within the gate electrode level region form an equal number of PMOS and NMOS transistor devices.

Title
Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
Application Number
12/563042
Publication Number
7932545 (B2)
Application Date
September 18, 2009
Publication Date
April 26, 2011
Inventor
Michael C Smayling
Fremont
CA, US
Scott T Becker
Scotts Valley
CA, US
Agent
Martine Penilla & Gencarella
Assignee
Tela Innovations
CA, US
IPC
H01L 27/10
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