07915134 is referenced by 1 patents and cites 14 patents.

A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

Title
Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
Application Number
11/970555
Publication Number
7915134 (B2)
Application Date
January 8, 2008
Publication Date
March 29, 2011
Inventor
Kunal Vaed
Poughkeepsie
NY, US
Anthony Kendall Stamper
Williston
VT, US
Robert Mark Rassel
Colchester
VT, US
Zhong Xiang He
Essex Junction
VT, US
Ebenezer E Eshun
Wappingers Falls
NY, US
Keith Edward Downes
Stowe
VT, US
Douglas Duane Coolbaugh
Essex Junction
VT, US
Anil Kumar Chinthakindi
Wappingers Falls
NY, US
Agent
Graham S Jones
H Daniel Schnurmann
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/20
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