07910958 is referenced by 124 patents and cites 260 patents.

A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Title
Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment
Application Number
12/563031
Publication Number
7910958 (B2)
Application Date
September 18, 2009
Publication Date
March 22, 2011
Inventor
Michael C Smayling
Fremont
CA, US
Scott T Becker
Scotts Valley
CA, US
Agent
Martine Penilla & Gencarella
Assignee
Tela Innovations
CA, US
IPC
H01L 27/10
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