07838424 is referenced by 26 patents and cites 49 patents.

An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.

Title
Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
Application Number
11/773277
Publication Number
7838424 (B2)
Application Date
July 3, 2007
Publication Date
November 23, 2010
Inventor
Jimmy Liang
Chung-Li
TW
Gene Wu
Dayuan Township
TW
Chien Hsiun Lee
Hsin-Chu
TW
Steven Hsu
Chung-Ho
TW
Tjandra Winata Karta
Hsinchu
TW
Agent
Slater & Matsil L
Assignee
Taiwan Semiconductor Manufacturing Company
TW
IPC
H01L 21/302
View Original Source