07836352 is referenced by 17 patents and cites 18 patents.

A method and apparatus is described herein for tracking errors for one of a plurality of lanes in a link, tracking errors for the link, and in the case of a root complex, tracking error correction messages. This information is used to determine the suitability for use of a lane and to determine if correction action is needed. In one embodiment, this method and apparatus is used with PCI Express interconnects.

Title
Method and apparatus for improving high availability in a PCI express link through predictive failure analysis
Application Number
11/479417
Publication Number
7836352 (B2)
Application Date
June 30, 2006
Publication Date
November 16, 2010
Inventor
Hanh Hoang
Sunnyvale
CA, US
Guru Rajamani
Sunnyvale
CA, US
Surena Neshvad
Hillsboro
OR, US
Debendra Das Sharma
Santa Clara
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 11/00
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