07805480 is referenced by 17 patents and cites 39 patents.

A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates and randomizes a polynomial quotient used for computation of a polynomial remainder. The randomizing error injected into the approximate polynomial quotient is limited to a few bits, e.g. less than half a word. The computed polynomial remainder is congruent with but a small random multiple of the residue, which can be found by a final strict binary field reduction by the modulus. In addition to a computational unit and operations sequencer, the computing hardware also includes a random or pseudo-random number generator for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks.

Title
Randomized modular polynomial reduction method and hardware therefor
Application Number
11/203939
Publication Number
7805480 (B2)
Application Date
August 15, 2005
Publication Date
September 28, 2010
Inventor
Michel Douguet
Marseilles
FR
Vincent Dupaquis
Biver
FR
Agent
Schwegman Lundberg & Woessner P A
Assignee
Atmel Rousset S
FR
IPC
G06F 7/72
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