07774726 is referenced by 9 patents and cites 111 patents.

Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the placement of dummy fill, in which dummy fill is added to certain layers of the IC to reduce process variations caused by other layers in the semiconductor devices. To accomplish this, layers in the design that cannot accommodate dummy fill are modeled to determine their topological variations. Other layers that are capable of receiving dummy fill are then analyzed to receive the correct quantity and distribution of dummy fill to correct for the topological variations from the non-dummy fill layers.

Title
Dummy fill for integrated circuits
Application Number
11/678542
Publication Number
7774726 (B2)
Application Date
February 23, 2007
Publication Date
August 10, 2010
Inventor
David White
San Jose
CA, US
Agent
Vista IP Law Group
Assignee
Cadence Design Systems
CA, US
IPC
G06F 17/50
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