07749886 is referenced by 8 patents and cites 154 patents.

A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.

Title
Microelectronic assemblies having compliancy and methods therefor
Application Number
11/643021
Publication Number
7749886 (B2)
Application Date
December 20, 2006
Publication Date
July 6, 2010
Inventor
David Ovrutsky
Ashkelon
IL
Belgacem Haba
Saratoga
CA, US
Guilian Gao
San Jose
CA, US
Vage Oganesian
Palo Alto
CA, US
Agent
Lerner David Littenberg Krumholz Mentlik
Assignee
Tessera
CA, US
IPC
H01L 21/44
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