07743233 is referenced by 12 patents and cites 27 patents.

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Title
Sequencer address management
Application Number
11/100032
Publication Number
7743233 (B2)
Application Date
April 5, 2005
Publication Date
June 22, 2010
Inventor
James Charles Abel
Phoenix
AZ, US
James Paul Held
Portland
OR, US
Sanjiv M Shah
Champaign
IL, US
David K Poulsen
Champaign
IL, US
John L Reid
Portland
OR, US
Ryan N Rakvic
Palo Alto
CA, US
Scott Dion Rodgers
Hillsboro
OR, US
Baiju V Patel
Portland
OR, US
Douglas M Carmean
Beaverton
OR, US
Prashant Sethi
Folsom
CA, US
Jason W Brandt
Austin
TX, US
Xiang Zou
Beaverton
OR, US
Per Hammarlund
Hillsboro
OR, US
John Shen
San Jose
CA, US
Bryant Bigbee
Scottsdale
AZ, US
Shivnandan D Kaushik
Portland
OR, US
Richard A Hankins
San Jose
CA, US
Gautham N Chinya
Hillsboro
OR, US
Hong Wang
Fremont
CA, US
Agent
David P McAbee
Assignee
Intel Corporation
CA, US
IPC
G06F 9/00
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