07736916 is referenced by 73 patents and cites 124 patents.

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Title
System and apparatus for using test structures inside of a chip during the fabrication of the chip
Application Number
11/762944
Publication Number
7736916 (B2)
Application Date
June 14, 2007
Publication Date
June 15, 2010
Inventor
James S Vickers
San Jose
CA, US
Gary L Steinbrueck
Wappingers
NY, US
Nader Pakdaman
Monte Sereno
CA, US
Jose J Estabil
Weston
CT, US
Majid Aghababazadeh
San Jose
CA, US
Agent
Mahamedi Paradice Kreisman
Assignee
tau Metrix
CA, US
IPC
H01L 21/00
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