07702986 is referenced by 76 patents and cites 21 patents.

Method and apparatus for generating codewords with variable length and redundancy from a single Low-Density Parity-Check (LDPC) code with variable length input words. A mother code for encoding data words is generated based on a parity-check matrix, wherein the mother code is adjusted to reflect the size of the data word to be encoded. A generator matrix applies the mother code to data words to produce codewords for transmission. In one embodiment, a reduction criteria is determined and the size of the generator matrix reduced in response. The corresponding parity-check matrix is applied at the receiver for decoding the received codeword.

Title
Rate-compatible LDPC codes
Application Number
10/299374
Publication Number
7702986 (B2)
Application Date
November 18, 2002
Publication Date
April 20, 2010
Inventor
Jay Rod Walton
Carlisle
MA, US
Nagabhushana Sindhushayana
San Diego
CA, US
John W Ketchum
Harvard
MA, US
Bjorn A Bjerke
Boston
MA, US
Agent
Larry J Moskowitz
Assignee
Qualcomm Incorporated
CA, US
IPC
H03M 13/00
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