07700466 is referenced by 94 patents and cites 3 patents.

In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

Title
Tunneling effect transistor with self-aligned gate
Application Number
11/828740
Publication Number
7700466 (B2)
Application Date
July 26, 2007
Publication Date
April 20, 2010
Inventor
Jack A Mandelman
Flat Rock
NC, US
Kangguo Cheng
Beacon
NY, US
Roger A Booth Jr
Wappingers Falls
NY, US
Agent
H Daniel Schnumann
Scully Scott Murphy & Presser P C
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/461
H01L 21/302
H01L 21/4763
H01L 21/3205
H01L 21/36
H01L 21/20
H01L 21/76
H01L 21/425
View Original Source