07676012 is referenced by 7 patents and cites 13 patents.

A controllable delay clock buffer that provides spread spectrum modulation of the output signals with zero cycle slip includes a PLL having a PLL loop filter that comprises an RC network. A clock signal is input to the PLL, and a SS modulation frequency is injected into the capacitor of the PLL loop filter. The SS signal is provided by a secondary charge pump that produces a programmable waveform such as a square wave or a stair case square wave current signal. The programmable waveform is integrated by the loop filter capacitor to form a corresponding triangular or trigonal waveform which varies the input to the VCO of the PLL to define a frequency modulation profile that has a corresponding triangular or trigonal envelope. The bandpass profile of the SS modulation signal is at a higher frequency range than the lowpass profile of the PLL, so that the SS waveform profile is not distorted or cancelled by the PLL.

Title
Spread spectrum controllable delay clock buffer with zero cycle slip
Application Number
10/831017
Publication Number
7676012 (B1)
Application Date
April 22, 2004
Publication Date
March 9, 2010
Inventor
Werner Hoeft
Santa Clara
CA, US
Sushil Kumar
Bangalore
IN
Dipankar Mandal
Bangalore
IN
Dan I Hariton
Santa Clara
CA, US
Narendar Venugopal
Santa Clara
CA, US
Agent
Howard Cohen
Harris Zimmerman
Assignee
Pulsecore Semiconductor
CA, US
IPC
H03D 3/24
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