07669035 is referenced by 22 patents and cites 30 patents.

A processing system includes a communication bus. a controller, an Input/Output (“I/O”) block, and reconfigurable logic segments (e.g., reconfigurable units). Individually reconfigurable logic segments are part of a single chip. A communication bus is in electrical communication with the logic segments. A first logic segment communicates to a Second logic segment over the communication bus. Reconfiguration can partition a first logic segment into a second and a third logic segment where the smaller logic segments are in electrical communication with the communication bus. Resources are dynamically reallocated when reconfigurable units are either combined or partitioned. More specifically, both partitioning a logic segment and combining two or more logic segments can change the bus width allocated to a reconfigurable unit and the quantity of logic gates in the reconfigured unit. As a result of a reconfiguration, a logic segment's embedded resources can change. The processing system provides high chip utilization throughout the chip's operation.

Title
Systems and methods for reconfigurable computing
Application Number
11/40177
Publication Number
7669035 (B2)
Application Date
January 21, 2005
Publication Date
February 23, 2010
Inventor
Dianne J Turney
Woburn
MA, US
Joshua Young
Boston
MA, US
Agent
Goodwin Procter
Assignee
The Charles Stark Draper Laboratory
MA, US
IPC
G06F 13/00
G06F 9/00
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