07657708 is referenced by 6 patents and cites 83 patents.

Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal activates only the cache dataram that stores the needed data.

Title
Methods for reducing data cache access power in a processor using way selection bits
Application Number
11/505869
Publication Number
7657708 (B2)
Application Date
August 18, 2006
Publication Date
February 2, 2010
Inventor
Ryan C Kinter
Sammamish
WA, US
Matthias Knoth
San Jose
CA, US
Agent
Sterne Kessler Goldstein & Fox PLLC
Assignee
MIPS Technologies
CA, US
IPC
G06F 12/00
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