07652498 is referenced by 42 patents and cites 94 patents.

Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit.

Title
Integrated circuit with delay selecting input selection circuitry
Application Number
11/769701
Publication Number
7652498 (B2)
Application Date
June 27, 2007
Publication Date
January 26, 2010
Inventor
Jason Redgrave
Mountain View
CA, US
Brad Hutchings
Provo
UT, US
Agent
Adeli & Tollen
Assignee
Tabula
CA, US
IPC
H03K 19/173
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