07650448 is referenced by 40 patents and cites 572 patents.

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Title
I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
Application Number
12/8543
Publication Number
7650448 (B2)
Application Date
January 10, 2008
Publication Date
January 19, 2010
Inventor
Robert Münch
Karlsruhe
DE
Martin Vorbach
Karlsruhe
DE
Agent
Kenyon & Kenyon
Assignee
Pact XPP Technologies
DE
IPC
G06F 15/76
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