07636408 is referenced by 7 patents and cites 8 patents.

An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.

Title
Reliable startup and steady-state of estimation based CDR and DFE
Application Number
11/445781
Publication Number
7636408 (B2)
Application Date
June 1, 2006
Publication Date
December 22, 2009
Inventor
Gabriel C Risk
Palo Alto
CA, US
Drew G Doblar
San Jose
CA, US
Jason H Bau
Mountain View
CA, US
Agent
Meyertons Hood Kivlin Kowert & Goetzel P C
Rory D Rankin
Assignee
Sun Microsystems
CA, US
IPC
H04L 7/00
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