07593263 is referenced by 113 patents and cites 302 patents.

A method for data storage includes providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency. An item of data intended for storage in the memory is divided into first and second parts. The first part is stored in the first memory cells and the second part is stored in the second memory cells. In response to a request to retrieve the item of data from the memory, the first part is read from the first memory cells and provided as output. The second part is read from the second memory cells, and provided as output subsequently to outputting the first part.

Title
Memory device with reduced reading latency
Application Number
11/958011
Publication Number
7593263 (B2)
Application Date
December 17, 2007
Publication Date
September 22, 2009
Inventor
Ofir Shalvi
Ra'anana
IL
Gil Semo
Tel-Aviv
IL
Dotan Sokolov
Ra'anana
IL
Agent
Darby & Darby P C
Assignee
Anobit Technologies
IL
IPC
G11C 16/04
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