07580443 is referenced by 35 patents and cites 9 patents.

In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

Title
Clock generating method and clock generating circuit
Application Number
11/331154
Publication Number
7580443 (B2)
Application Date
January 13, 2006
Publication Date
August 25, 2009
Inventor
Makoto Funatsu
Akiruno
JP
Akio Katsushima
Kodaira
JP
Takashi Nakamura
Kokubunji
JP
Yasuhiro Uemura
Sagamihara
JP
Agent
Miles & Stockbridge P C
Assignee
Renesas Technology
JP
IPC
H04B 1/69
View Original Source