07548996 is referenced by 29 patents and cites 51 patents.

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

Title
Data streamer
Application Number
11/224738
Publication Number
7548996 (B2)
Application Date
September 12, 2005
Publication Date
June 16, 2009
Inventor
Radhika Thekkath
Palo Alto
CA, US
Eric Rehm
Bainbridge Island
WA, US
Ashok Raman
San Jose
CA, US
John Poole legal representative
Salem
OR, US
John O Donnell
Seattle
WA, US
Toru Nojiri
Tokyo
JP
Yatin Mundkur
Sunnyvale
CA, US
Woobin Lee
Lynnwood
WA, US
Gregorio Gervasio
Sunnyvale
CA, US
Benjamin Cutler
Seattle
WA, US
Christopher Basoglu
Bothell
WA, US
David Baker
Chapel Hill
NC, US
Agent
Sofer & Haroun
Assignee
Equator Technologies
CA, US
Hitachi
JP
IPC
G06F 13/28
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