07548430 is referenced by 120 patents and cites 141 patents.

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

Title
Buildup dielectric and metallization process and semiconductor package
Application Number
11/497617
Publication Number
7548430 (B1)
Application Date
August 1, 2006
Publication Date
June 16, 2009
Inventor
David Jon Hiner
Chandler
AZ, US
Sukianto Rusli
Phoenix
AZ, US
Ronald Patrick Huemoeller
Chandler
AZ, US
Agent
Serge J Hodgson
Gunnison McKay & Hodgson L
Assignee
Amkor Technology
AZ, US
IPC
H05K 7/00
View Original Source