07545041 is referenced by 3 patents and cites 14 patents.

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

Title
Techniques for patterning features in semiconductor devices
Application Number
11/337411
Publication Number
7545041 (B2)
Application Date
January 23, 2006
Publication Date
June 9, 2009
Inventor
Richard Stephan Wise
New Windsor
NY, US
Dirk Pfeiffer
Dobbs Ferry
NY, US
Arpan P Mahorowala
Bronxville
NY, US
Steven J Holmes
Guilderland
NY, US
Katherina E Babich
Chappaqua
NY, US
Scott D Allen
Wappingers Falls
NY, US
Agent
Ryan Mason & Lewis
Daniel P Morris Esq
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 29/40
H01L 23/52
H01L 23/48
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