07485562 is referenced by 94 patents and cites 234 patents.

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

Title
Method of making multichip wafer level packages and computing systems incorporating same
Application Number
11/28374
Publication Number
7485562 (B2)
Application Date
January 3, 2005
Publication Date
February 3, 2009
Inventor
Wei Zhou
Singapore
SG
Suangwu Huang
Singapore
SG
Suan Jeung Boon
Singapore
SG
Yong Loo Neo
Singapore
SG
Meow Koon Eng
Singapore
SG
Yong Poo Chia
Singapore
SG
Siu Waf Low
Singapore
SG
Swee Kwang Chua
Singapore
SG
Agent
TraskBritt
Assignee
Micron Technology
ID, US
IPC
H01L 21/44
H01L 23/48
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