07433231 is referenced by 94 patents and cites 9 patents.

Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

Title
Multiple select gates with non-volatile memory cells
Application Number
11/411376
Publication Number
7433231 (B2)
Application Date
April 26, 2006
Publication Date
October 7, 2008
Inventor
Seiichi Aritome
Boise
ID, US
Agent
Brooks Cameron & Huebsch PLLC
Assignee
Micron Technology
ID, US
IPC
G11C 16/04
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