07420272 is referenced by 53 patents and cites 396 patents.

A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the electronic component; coupling the first surface of the electronic component to a first surface of a lower dielectric strip; coupling the second surface of the electronic component to a first surface of an upper dielectric strip; forming lower via apertures through the lower dielectric strip to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component; forming upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component; filling the lower and upper via apertures with an electrically conductive material to form lower and upper vias electrically coupled to the first and second selected bond pads of the plurality of bond pads on the first surface of the electronic component.

Title
Two-sided wafer escape package
Application Number
11/784979
Publication Number
7420272 (B1)
Application Date
April 9, 2007
Publication Date
September 2, 2008
Inventor
David Hiner
Chandler
AZ, US
Russ Lie
Phoenix
AZ, US
Ronald Patrick Huemoeller
Chandler
AZ, US
Agent
Serge J Hodgson
Gunnison McKay & Hodgson L
Assignee
Amkor Technology
AZ, US
IPC
H01L 23/12
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