07363598 is referenced by 23 patents and cites 79 patents.

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Title
Dummy fill for integrated circuits
Application Number
10/947500
Publication Number
7363598 (B2)
Application Date
September 22, 2004
Publication Date
April 22, 2008
Inventor
David White
Cambridge
MA, US
Vikas Mehrotra
Fremont
CA, US
Taber H Smith
Fremont
CA, US
Agent
Bingham McCutchen
Assignee
Cadence Design Systems
CA, US
IPC
G06F 17/50
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