07360179 is referenced by 193 patents and cites 79 patents.

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Title
Use of models in integrated circuit fabrication
Application Number
11/142606
Publication Number
7360179 (B2)
Application Date
May 31, 2005
Publication Date
April 15, 2008
Inventor
David White
Cambridge
MA, US
Vikas Mehrotra
Fremont
CA, US
Taber H Smith
Fremont
CA, US
Agent
Bingham McCutchen
Assignee
Cadence Design Systems
CA, US
IPC
G06F 19/00
G06F 17/50
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