07356554 is referenced by 6 patents and cites 1 patents.

A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.

Title
Variable fixed multipliers using memory blocks
Application Number
11/168984
Publication Number
7356554 (B1)
Application Date
June 27, 2005
Publication Date
April 8, 2008
Inventor
Benjamin Esposito
Oviedo
FL, US
Asher Hazanchuk
Sunnyvale
CA, US
Agent
Martine Penilla & Gencarella
Assignee
Altera Corporation
CA, US
IPC
H03K 19/177
G06F 7/42
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